The present invention relates to data communication circuits. More particularly, the present invention relates to a data communication circuit having a transmit first-in-first-out (FIFO) buffer, which assists in re-transmitting aborted data frames.
Data communication circuits such as network devices and telecommunications circuits typically have several communication channels for connecting to multiple devices such as workstations, telephone and television systems, video teleconferencing systems and other facilities over common data links or carriers. A channel is a logical path from one source to one destination and can be unidirectional or bidirectional. A data routing circuit, such as a direct memory access (DMA) controller, routes data to and from each channel. The data is usually grouped into frames, or packets, of any size. Each channel includes a data interface controller, such as a serial wide area network (SWAN) controller or a local area network (LAN) controller that is coupled to the data routing circuit for controlling transmission of its respective data over the data link or carrier.
Data interface controllers are often configured to transmit frames or packets of data having an arbitrary length at a fixed speed. For example, a WAN controller may transmit an Internet Protocol (IP) packet over a fixed speed Interactive Services Digital Network (ISDN) Basic Rate Interface (BRI) using high level data link control (HDLC) framing. Alternatively, a LAN controller such as an Ethernet controller may transmit an IP packet over a fixed speed 10 or 100 Mbps LAN, for example.
In these applications, it is common to use a first-in-first-out (FIFO) memory for buffering transmit and receive data between the data routing circuit and data interface controller. Each communication channel typically has its own transmit FIFO and its own receive FIFO. A typical FIFO uses a dual port random access memory (RAM) for storing the data. One port is used by the data interface controller and the other port is used by the data routing circuit. During a transmit operation, the data routing circuit writes the data packets to one end of the FIFO at a data routing circuit transmission rate, and the data interface controller reads the packets at the other end of the FIFO at the rate of the fixed speed data interface.
The FIFO is needed because the data routing circuit transmission rate is generally substantially higher on average than the rate of the fixed speed data interface. Also, the data routing circuit is subject to xe2x80x9cgapsxe2x80x9d in its ability to feed the FIFO because of memory access latencies, contention with other master devices that are coupled to the memory bus and control logic overhead.
Each FIFO is accompanied by control logic that requests service from the data routing circuit when the amount of data in the FIFO drops below a certain point, such as an xe2x80x9calmost emptyxe2x80x9d threshold. This amount is chosen such that even with worst-case memory access latency, bus contention and control overhead the data in the FIFO will not be completely drained by the fixed speed data interface. The fixed speed data interface controller is typically configured to start extracting data from the FIFO only after a set amount of data is in the FIFO. Once the data interface controller has started transmitting, it must continue transmitting until the end of the frame. During a receive operation, the data interface controller writes the data packets at one end of the FIFO at the rate of the fixed speed data interface, and the Data routing circuit reads the data packets from the other end of the FIFO at the DMA transmission rate. The Data routing circuit waits until there is a sufficient amount of data stored in the FIFO before reading a data packet from the FIFO. This allows the data routing circuit to read an entire packet or frame from the FIFO in a xe2x80x9cburst modexe2x80x9d at the Data routing circuit transfer rate.
Ethernet networks are currently the most popular local area networks (LANs). In half-duplex mode, data transfer collisions over an Ethernet channel occur on a regular basis. Occasionally, excessive collisions or late collisions occur when the channel is broken or overloaded, for example. When excessive or late collisions occur, the data frame being transmitted from the transmit FIFO buffer is aborted. The software used by higher level protocols attempts to determine which data frame was aborted and how to respond. For example, the aborted data frame may be recovered through redundancy or other known methods.
Typically, it would be beneficial to re-transmit the aborted data frame. However, since several data frames may be queued-up in the transmit FIFO buffer, the software used by the higher level protocols has no way of knowing which data frame was aborted. In some systems, the software makes a xe2x80x9cguessxe2x80x9d as to which data frame or frames should be re-transmitted. This could result in some xe2x80x9cgoodxe2x80x9d data frames being transmitted twice. Also, if higher level protocols are used to determine the missing packet, large data transmission latencies could result.
The transmit FIFO buffer and communication circuit of the present invention addresses these and other problems and offers other advantages over the prior art.
One aspect of the present invention is directed to a data transmission buffer circuit for buffering communication data, which is divided into a plurality of multiple-bit data frames that have a start and an end. The buffer circuit includes a first-in-first-out (FIFO) buffer and a frame counter. The FIFO buffer has a write port and a read port. The write port includes a data input, a write control input and an end-of-frame flag input, which indicates whether data on the data input includes the end of one of the data frames. The read port includes a data output, a read control input, and an end-of-frame flag output, which indicates whether data on the data output includes the end of one of the data frames. The frame counter is coupled to the write port and the read port and generates a frame count output, which represents a number of the data frames that are stored in the FIFO buffer.
Another aspect of the present invention is directed to a communications subsystem for transmitting communication data, which is divided into a plurality of multiple-bit data frames that have a start and an end. The subsystem includes a data bus, a register bus, a processor, a data routing circuit, a data interface controller, a transmit first-in-first-out (FIFO) buffer, and a frame counter. The processor and the data routing circuit are coupled to the data bus and the register bus. The transmit FIFO buffer is coupled between the data routing circuit and the data interface controller and has storage locations adapted to store successively received ones of the data frames from the data routing circuit. The frame counter has a count control input, which is coupled to the transmit FIFO buffer, and a count output, which is coupled to the register bus for access by the processor and represents a number of the data frames that are stored in the transmit FIFO.
Yet another aspect of the present invention is directed to a method of re-transmitting an aborted one of a plurality of multiple-bit data frames in a communications subsystem. The method includes: retrieving successive ones of the data frames from a memory; transferring the successive ones of the data frames to a transmit first-in-first-out buffer; transmitting the successive ones of the data frames from the transmit FIFO buffer to a communications channel sequentially, wherein transmission of the aborted data frame is discontinued; counting a number of the successive ones of the data frames that remain in the transmit FIFO after transmission of the aborted data frame has been discontinued; identifying the aborted data frame based on the number; and transferring the aborted data frame from the memory to the transmit FIFO buffer again, after the step of identifying, for re-transmission through the channel.